Design of stable and low power 9T SRAM cell with improved read and write speed

Nowadays with the advancement of technology, the requirement for high speed circuits and memories with low leakage power consumption by keeping stability has been increased. In this paper, a stable 9T SRAM cell which is improved for high speed applications with low leakage power consumption has been suggested. In this scheme, two techniques including the isolation of read and write paths and the “stack effect” technique are used simultaneously to improve read and write performance. The results of simulations in 32 nm CMOS technology indicate that the proposed cell is in the category of high speed cells. Meanwhile, the leakage power of the proposed cell has been reduced 16% to 48% compared with high speed cells. It should be noted that the read stability of the proposed cell has nearly become two times greater than the conventional 6T SRAM cell.