Blockage of Lateral Electric Field from Source/Drain Regions to Improve Short Channel Effects in Nano-SOI device

This paper has presented a new method for the improvement of short channel effects with no complexity in the fabrication flow of Nanoscale silicon-on-insulator (SOI) devices. The basic idea in this paper is realization of a U-shaped oxide using Si3N4 material inside the buried oxide and channel region. The lateral electric field lines path from source/drain deviates after meeting with the embedded oxide. As a result, less electric field lines will get the ability to go through the oxide and to reach the channel region. A double ability is caused by increase in effective thermal conduction of the proposed structure in high temperature applications. A comparison between the proposed structure and conventional structure shows that the important parameters such as short channel effects, lattice temperature, electric field, electron mobility and drain conductance have been effectively improved promising the superiority of the proposed device. The structures under study in this paper have been simulated by ATLAS simulator which is one of the commercial products of SILVACO family.