New Dynamic Circuit for Low Power Tag Comparator Design

In this paper, a new dynamic circuit is proposed to reduce power consumption of tag comparators. To reduce the power consumption in the proposed dynamic circuit, NMOS transistors are used to precharge the dynamic node. In this way, voltage swing on the dynamic node is decreased and hence the power consumption is reduced. Simulation of wide fan-in OR gates and 40-bit tag comparators are done using HSPICE simulator in a 90nm CMOS technology model. Simulation results exhibit 42% power reduction and 1.68× noise-immunity improvement at the same delay compared to the conventional dynamic circuit for 32-bit OR gates. Moreover, simulation results demonstrate 52% and 16% reduction in the power consumption and delay of the proposed tag comparator, respectively, at the same noise immunity compared to the conventional one