Reliability-Enabled Routing in Congestion-Aware Networks-on-Chip

The efficiency of networks on chip (NoC) is affected by related routing algorithms. Network congestion has a negative impact on the performance of on-chip networks due to the increased packet latency. One of the key objectives design of NoC is reliability against failure. For a NoC to be robust, achieving better performance, and tolerating faults, two key functions need to be investigated: (a) the ability to avoid congested paths and balancing the traffic workloads, and (b) the ability to tolerate faults as well as proceeding to provide system functionality against physical impairment. For this purpose, a cost model for route selection with greater reliability and less congestion has been proposed. In this model, at first a congestion-aware routing algorithm is deployed based on the Q-learning approach to check congested areas in the network, then adjacent links are considered to deal with reliability. Finally, given the importance of the reliability, high weight is assigned to this parameter, and the path with the lowest cost is selected to forward packets. Simulation results show that the proposed approach outperforms state-of-the-art Bi-LCQ algorithm under two traffic patterns.