Reliability Evaluation of Digital Circuits Using Probabilistic Signal Flow Graphs

Although reducing the size of transistors increased their capabilities considerably, but also resulted in more susceptibility to transient errors. Thus, detecting the sensitive nodes of digital circuits is essential for designing digital circuits at few nanometers. On the other hand, increasing the number of logic gates, transient error types and several error propagation mechanisms in digital circuits, results in considerable complexity in reliability evaluation. Thus, scalability, computational complexity, runtime, accuracy and memory consumption should be taken into account for such evaluation. In this paper, using the concept of the probabilistic signal flow graphs, a new approach is proposed to evaluate the reliability of digital circuits which demonstrates good accuracy, runtime and high level of scalability. Probabilistic evaluation of re-convergent paths, using fixed point theorem and using the sparsity of matrices are features of the proposed approach. Using the proposed approach, the reliability of circuits with feedback and sequential circuits is also evaluated. Simulation results show that the computational complexity of the proposed approach for a combinational and sequential circuit with N nodes is O(N0.85) and O(N0.99) respectively.