Design and Optimization of Input-Output Block using Graphene Nano-ribbon Transistors

In the electronics industry, scaling and optimization is final goal. But, according to ITRS predictions, silicon as basic material for semiconductors, is facing physical limitation and approaching the end of the path. Therefore, researchers are looking for the silicon replacement. Until now, carbon and its allotrope, graphene, look to be viable candidates. Among different circuits, IO block is a needed ingredient for electronic systems and needs to be re-designed and optimized. In this paper, goal is feasibility analysis and design of IO blocks using graphene field effect transistors. Using these transistors, each ingredient is designed, simulated and analyzed using the HSPICE tool. Then, these ingredients are combined together and the graphene-based IO block is implemented. Similar to graphene IO, silicon- based IO block is also designed and results are compared. It indicated that propagation delay is 299.9ps with 10% edge roughness, which is 32% faster compared to silicon counterpart.