Four-port non-blocking switch for reducing insertion loss in hybrid photonic networks-on-chip

A multi-processor architecture was proposed to address power consumption limitations in chips in order to increase performance and lower power consumption. In this architecture, the highest power consumption comes from the chip connections. Optical connections can reduce power consumption and increase performance via a new architecture called photonic network-on-chips, which are capable of utilizing the benefits of optical signals and elements for data transfer. This paper proposes a 4×4, non-blocking photonic switch to improve physical layer parameters by increasing photonic network performance. The insertion loss and energy dissipation of the proposed switch were compared to three switches: Original, StraightPath, and Symmetric switches. The results indicated that, in a mesh topology, the proposed switch reduced loss for the GTC, Cactus, Tornado, and MADbench by 28.22, 24.46, 28.72, and 29.20%, respectively, when compared to the Original switch. According to PhoenixSim simulation results, the proposed switch reduced insertion loss and energy dissipation in photonic network-on-chips when compared to the three comparison switches.