Designing Wide-Band Mixed Delay-Line for using in Delay Locked Loop

Supporting the highest bandwidth data rates among new generation of communication devices requires advanced clock management technology such as DL (Delay Line). By introducing object internet increase of the system clock frequency poses some challenges in generating and distributing of the clock with low uncertainty and power, as clocks determine the overall performance of the chip. The generated signal quality determines by several factors as frequency, phase, period, jitter and clock variations. Both analog and digital circuits have some limitations which make it impossible to achieve high quality clock. One of the proposed solutions for performance improvement of DLs is the utilization of both analog and digital circuits in one system. In this thesis a low jitter and wide operation range Mixed-Mode Delay Line presented. Body feed technique and proper bias circuit are used in the proposed multiphase Mixed Controlled Delay-Line (MMCDL) to widen applicable range of control voltage, allow rail-to-rail operation and overcome the nonlinearity of the conventional current starved delay element. Furthermore, two single ended current starved inverters are utilized in a differential structure to minimize the effect of the power supply and the substrate noise. In this way jitter and static phase error specifications are improved. The designed circuit is simulated in ADS software, using TSMC 0.18 um CMOS process at 1.8V supply voltage. Simulation outcomes indicate that the frequency range of the suggested DL is 80-920 MHz. The rms jitter and power dissipation of the designed circuit at 920 MHz are 3.7psec and 3.9 mW respectively.