Investigating the role of nanoelectronic memory resistaor in the future of hardware security

Memristor is the forth fundamental circuit element that has received considerable attention due to its possible applications in future nanoscale systems. This paper describes the advantages that this nanoscale elements and nanotechnology may offer in the implementation of encryption algorithms in hardware and embedded platforms. To demonstrate this subject,, an Advanced Encryption Standard core was designed and implemented in both CMOS and hybrid CMOS/nanotechnology. The resistance of both implementation s against power analysis attack was evaluated and compared. It was demonstrated that hybrid CMOS/Nano circuit provides considerable improvement over implementation with regular CMOS circuits in terms of power consumption and resistance against Differential Power Analysis (DPA) attacks without needing to apply any costly algorithmic countermeasure or using any extra circuit. Simulations were carried out using HSPICE and Cadence Spectre and the attack algorithm was written in MATLAB. The results obtained in this paper can be used in enhancing the security of the future generation of urban and commercial smart information and communication systems.