A new design of low power and high-speed 1-bit full adder cells for digital signal processors

Computational circuits, including full adders, are used as an important base for the design and implementation of many applications such as adaptive filters, modulators, and fuzzy logic controllers. Having an optimal design with the aim of increasing the speed and reducing the power consumption can be the reason for the progress of industries and also improve the military power of the country. This article provides a new implementation for a 1-Bit Full-Adder Cell with 10 CMOS transistors. This design presents a higher speed and lowers power consumption compared to other standard 1-bit full adder cells. Eliminating an inverter from the critical path accounts for its high speed while reducing the number and magnitude of the cell capacitances, in addition to eliminating the short circuit power component, account for its low power consumption. The simulation results show the advantages of the proposed design. In this paper, 0.18 μm technology, temp = 27 °C, a 1.8 V power supply, and TT corner are used. The software used in this article is Cadence IC Design, which will show the proposed circuit will save 9% of energy consumption.