Reduce Disturbance Code: Reducing Energy Consumption in a 3D ICs by Applying Error Detecting and Correcting Codes

In the structure of 3D ICs, several layers of components are placed on top of each other. The connections between these layers is through vertical layers of interconnections. One of the major challenges that can threaten the reliability of a grid-based system on a three-dimensional chip is crosstalk Fault. Crosstalk fault in 3D ICs, is depending on the ranking of their transition patterns that greatly challenges the reliability, efficiency and Energy of the 3D ICs. The purpose of this paper is to present and investigate coding, called disturbance coding. By reducing the most delayed pattern, this coding mechanism reduces crosstalk in 3D ICs with the least possible overhead and power consumption. The basic idea is that first the data to be transferred from layer x to layer y is placed in the intermediates in the layer x solutions, then the counter unit measures the amount and counts of 4C class transitions and gives a signal to the unit. The crossbar will specify the final arrangement of the data to be sent to the y layer. Simultaneously with sending this control signal, another signal will be sent through this unit to the decoder in the receiver to retrieve the original data by this section. The simulation results show the amount of overhead compared to other methods.