A Low Voltage, Time-Domain, Full Range, CMOS Winner-Take-All Circuit.

In this paper a rail-to-rail time-domain CMOS winner take all (WTA) circuit is proposed. To convert the analog voltage to a delay time a voltage controlled delay line is employed. In order to implement a full range time domain winner take all, a linear rail-to-rail delay element is employed. A positive feedback loop is utilized to reduce the decision time. Employing a linear rail-to-rail delay element, improves the precision and dynamic range of the entire winner take all circuit. In addition, the proposed circuit is employed a new phase detector to reduce transistors have been utilized in the circuit and decrease the parasitic elements of VCDLs. As a result the proposed circuit is designed to operate in subthreshold region to 0.3V. Based on the proposed structure, a 3-input WTA circuit has been designed and simulated in a 0.18um CMOS technology with a 1V supply voltage. The simulated results confirm that the power consumption of the presented winner take all circuit is 0.72uW at 10MHz clock frequency.The simulation results show the Figure of Merit of 2.4uW/MHz and 99.98% precision and the circuit operates to 0.38V supply voltage.