Design of a Multipurpose Nanowire Transistor for Basic Logic Gates Implementation

In this paper, a multipurpose nanowire transistor for the implementation of logical gates of NOT, NAND, and NOR is designed. In this design, a silicon nanowire with (7nm×7nm) area surrounded by silicon dioxide is used and there are three separated gates on that oxide. A simulation method is based on solving self-consistent Schrodinger-Poisson equations. The type of logical function can be specified by the control gate voltage level without any changes in the hardware and circuit structure. By using this simulation method, the electric potential of channel, carrier densities, and electric current are calculated. The effects of each gate on the electric characteristics of the device are analyzed and investigated. The optimum value of channel impurity concentration is obtained for the logical function characteristics to be symmetrical. In addition, the noise margins are calculated. The results indicate that the designed transistor can lead to the development of future integrated circuits.