Dual-VDD System Design with Energy Efficient near-Threshold Voltage Level Converter

Multi-VDD design is one of the most effective lower-power design techniques. Multi-VDD VLSI circuits require voltage level converters to prevent high static power dissipation between different voltage islands. As the level conversion step imposes additional power and delay to the design, it is very important to optimize the level converter circuits for minimum power-delay product (PDP). This paper presents an energy efficient single supply level converter (SSLC) based on carbon nanotube FET (CNTFET) for near threshold dual-VDD circuits. CNTFET as an emerging nanotechnology is suitable for low-power and high-performance circuits design. The proposed SSLC is utilized in the structure of a modified low-power parallelized dual-VDD multiplier. Insertion of the proposed SSLC at the output stage of the multiplier significantly reduces static power and enhances the output driving capability. In the proposed SSLC, dynamically controlled source-body voltage reduces drain-induced barrier lowering (DIBL) effect. In addition, using dual-chirality CNTs leads to optimum static power and energy consumption. The simulation results, obtained using the Stanford CNTFET HSPICE model at 32nm feature size, indicate the superiority of the proposed dual-VDD parallel multiplier utilizing the proposed SSLC in terms of power and power-delay product (PDP) as compared to the single supply multiplier. It is worth mentioning that the proposed low-power multiplier improves static power, average power and PDP by almost 41 %, 42% and 33%, respectively, while maintaining almost the same throughput as compared to the single-supply multiplier.