Performance Optimization of an Electrostatically Doped Staggered Type Heterojunction Tunnel Field Effect Transistor with High Switching Speed and Improved Tunneling Rate

In this paper, we demonstrate an electrostatically dopedjunctionless tunnel field effect transistor which iscomposed of a staggered band alignment at theheterojunction. The proposed structure reduces thetunneling barrier width to have a higher on-sate currentusing Ge/GaAs heterojunction at the source-channelinterface. Due to the employment of electrostaticallydoped strategy for creating p+-n+ tunneling junction, theintroduced device has low temperature simple fabricationprocess. The device has on-state current of 1.5×10-4(A/μm), subthreshold swing of 5.15 mV/dec and on/offcurrent ratio of 1.56×1010, manifesting the design of afast switching device. In addition, statistical analysis isconducted to investigate the sensitivity of deviceperformance with respect to the variation of criticaldesign parameters. The results demonstrate that gateworkfunction and polarity gate bias are fundamentaldesign parameters and optimum value should bedetermined for them to assess efficient deviceperformance.