Design of a Low-Area, Low-Power and High-Speed Comparator in 65 nm FinFET Technology

In the present study, a new low-power and high-speed comparator circuit is designed in 65 nm fin field-effect transistor (FinFET) technology. Moreover, by properly using the capabilities of FinFET technology, the number of transistors is reduced, and subsequently, a smaller area is occupied. Replacing MOSFET transistors with FinFETs reduces the delay and power consumption of the circuit, so the overall performance is improved. The first innovation of the proposed design is that to reduce the size and power consumption, two transistors were removed and the back gates of two transistors were cross-coupled. The second innovation is the connection of back gates to other suitable points of the circuit that increase the speed of comparison. In this study, a supply voltage of 0.8 V is applied to the circuit to show that the proposed modifications with FinFET reduce the delay to 272 ps and power consumption to 6.7 µW.