Design of a novel congestion-aware communication mechanism for wireless NoC in multicore systems

Network-on-Chip (NoC) has emerged as leading interconnection backbone to integrate numerous blocks in a single chip. Although it offers a high-performance communication infrastructure by using integrated switch-based networks, the possible performance improvement of a conventional NoC is restricted by multi-hop communications due to high transmission latency and power consumption incurred by the data transmission between two distant cores.  In order to mitigate this problem, wireless NoC (WNoC) architecture has proposed as an alternative solution to design flexible, low-power, and high bandwidth communication infrastructures for the future multicore platforms. It is necessary to mention that wire-based interconnections are still highly effective for short distances communications. Therefore, hybrid WNoC architectures are emerged as scalable communication structure to alleviate the deficits of traditional NOC architecture for the modern multicore systems. The hybrid WNoC architecture provides energy efficient, high data rate and flexible communications for NoC architectures. In these architectures, each wireless router is shared by a set of processing cores. However, sharing links between cores increases congestion in the network that limits the performance and scalability of NoCs and affects the system to work at less than its peak gain. Moreover, the congestion can heightens network inefficiency when the network is scaled to more nodes. In this paper, we propose a novel congestion-aware mesh-based WNoC architecture to address these issues. We consider optimization of the system cost and performance, simultaneously. For congestion control, it is recommended to include a multi-path routing. This means that several routes are calculated and recorded for each destination and finally the traffic load is distributed. Paths are selected based on their scores, which are obtained dynamically. When a path is used to transmit packets, the score of that path is reduced so that fewer packets are sent from that path and more scored paths are used. This approach aims to the distribution of traffic loads on the paths. The performance of the proposed architecture has been evaluated and compared with notable WNoC architectures through comprehensive simulations. The experimental results demonstrated the effectiveness of the proposed design under both synthetic and realistic traffic patterns in terms of network throughput, latency, and energy consumption.