Synthesis Optimization of Arithmetic Circuits on Coarse-Grain Reconfigurable Architecture

The increasing capabilities of integrated circuits and the complexity of applications have led hardware design methods and tools to higher levels of abstraction. High-level synthesis is one of the key steps in increasing the level of abstraction, and the more concise the initial description in the intended application, the more efficient the high-level synthesis will be. Arithmetic applications are among the applications in which the initial input is very abstract. In recent years, extensive research has been conducted on the design of arithmetic reconfigurable architectures. Since, on the one hand, the effective use of these architectures depends on the existence of appropriate algorithms and tools to implement the design on the hardware, and on the other hand, research on the development of these algorithms has been very limited, this paper will present methods for optimizing the automated synthesis of arithmetic circuits on a coarse-grained reconfigurable architecture. These optimizations include mapping optimization, delay optimization, and area optimization. The platform chosen to execute the proposed algorithm is the DARA coarse-grained reconfigurable architecture, which is optimized for decimal arithmetic. The results show that implementing the TELCO benchmark on DARA using proposed optimizations entails about 30% gain in the area of the circuit.