Design of Novel Low-Power Single-Loop Sigma-Delta Modulator by Reduction of Amplifiers in the Loop-Filter for Speech Recognition Applications

In this paper, a novel general architecture for single-loop Sigma-Delta Modulator is presented by combination low-distortion and noise-coupled techniques for high-resolution low-power applications. The low-distortion technique in the proposed architecture makes its signal transfer function equal to one. In addition, the noise-coupled technique increases the order of quantization noise shaping at the modulator output. The purpose of using these techniques in design of the architecture is to increase the order of the modulator without needing to additional operational amplifiers during its circuit implementation to finally achieve a low-power modulator compared to similar ones. To reduce the required amplifiers, a second order infinite impulse response (IIR) filter was used instead of an integrator in the modulator loop. To evaluate the performance of the proposed structure, its implementation and simulation for speech recognition application, i.e., digital hearing aids, were performed in 180nm CMOS (complementary metal-oxide semiconductor) technology. For a third-order structure with a sampling rate of 64 and an input sine signal of -6dBFS and a sampling frequency of 2.56MHz, the signal to noise and distortion (SNDR) is 81.9dB and the dynamic range (DR) is 88dB. The power consumption of the modulator is 126.9 μW and its bandwidth is 20 KHz. The results of circuit and system level simulations prove its performance.