In this paper, a comparator is introduced for use in CMOS image sensor which can suppress the FPN noise of the pixel in addition to comparing voltages. Due to a large number of circuits in the column-parallel image sensors, this technique can help save power, silicon area, and imaging time by merging the noise suppression circuit in the data converter. Simulation results show that the proposed comparator for the input range of 0.7 to 1.7 volts with an accuracy of 1 mV can do the comparison and subtraction in 25 nanoseconds. The total power consumption of the comparator is about 64 microwatts, which has 1.8- & 2.5-volt power supply and removes FPN noise up to the range of 50 mV with good accuracy. Total noise referred to the input of the comparator for the bandwidth of 1 Hz to 1GHz was obtained 500µV. All circuits are designed in 0.18μm CMOS technology and simulated by Specter simulator.