New Dynamic Circuit for Design of High-Speed Register Files

The main portion of the delay and power in register files is related to read-out paths. The read-out paths are implemented using dynamic circuits to improve the performance of register files. Therefore, design of a high-speed and low-power dynamic circuit is necessary to achieve energy efficient register files for modern microprocessors. In this paper, a new dynamic circuit is presented to decrease the delay and power consumption of register files without considerable noise immunity degradation. In the proposed dynamic circuit, the supply voltage of the pull-down network (PDN) is lower than the main supply voltage to decrease the switching power consumption. In addition, the wide fan-in pull-down networks are implemented using the narrower networks to decrease the switching capacitance on the dynamic node and increase the circuit performance. A 64-word  32-bit 2-read, 1-write ported register file is implemented using the proposed circuit technique. Simulations are performed using HSPICE simulator in a 90-nm CMOS technology model. Simulation results demonstrate 45% and 31% reduction in delay and power consumption of the proposed register file respectively at the same noise immunity compared to the conventional register file.