Majlesi Journal of Telecommunication Devices
Volume:2 Issue: 2, Jun 2013

Nowadays, the volume of the data transported in telecommunication systems is noticeably growing, which means that the bandwidth required for data transmission is also increasing. However, due to high transmission speed of the data, those circuits are needed which can properly act at high speed (frequency). Clock and data recovery (CDR) circuit using bang-bang phase detector (BBPD) are widely used in communication systems mainly because of their high-frequency capabilities. However, bang-bang clock and data recovery (BBCDR) circuits are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). In this paper, first, architecture of BBCDR circuits is stated in addition to expressing basic concepts of clock and data recovery circuits. Since characteristics of frequency response of CDR are determined by jitter tolerance and jitter transfer characteristics, concepts of these characteristics are mentioned and the presented analyses are evaluated.

It has already been shown that in rate-constrained broadcast channels, under the assumption of independent Rayleigh fading channels for different receivers, the user capacity (i.e. the maximum number of users that can be activated simultaneously) scales with $\ln (P \ln n)/R_{\min}$ where $P$ is transmit power, $R_{\min}$ represents the minimum rate required for each receiver to be activated, and $n$ denotes the total number of receivers in the system. However, to achieve the aforementioned result, it is assumed that channel state information (CSI) is perfectly known to the receivers. In practical situations, the receivers do not have access to the true CSI and they only know estimated channels. In this paper, the effects of channel estimation is analyzed on the user capacity of rate-constrained broadcast channels. In particular, the Minimum Mean Square Error (MMSE) channel estimation scheme is considered and the effects of this estimation method on the user capacity is investigated. Under the assumption of independent Rayleigh fading channels for different receivers, it is shown that the user capacity scales with $\ln (\hat{\sigma}^2 P \ln n)/R_{\min}$ where $\hat{\sigma}^2$ denotes the variance of estimated channels and is determined by the MMSE channel estimation algorithm. As the received signal model is linear with respect to the fading channels, it is shown that the user capacity scaling law is unchanged and the difference is only a constant factor depending on the channel estimation scheme.

In this paper an overview of circuit techniques dedicated to design low-power low-voltage is presented. These techniques (a) dynamic threshold voltage MOSFET (DTMOS) (b) bulk-driven and (c) current-driven bulk (CDB) are applied to design low-power low-voltage and low-noise CMOS operational amplifier (op amp) using sub-threshold region of MOSFET for bio-medical instrumentation operating with a 0.6 V supply. The operational amplifier is designed and simulated using TSMC 0.18μm CMOS technology. With DTMOS technique, the open loop gain is 60.51 dB, the unity gain-bandwidth (UGBW) is 12.08 kHz, phase margin is 52.3 degree and power consumption is 53.21 nW. With bulk-driven technique, the open loop gain is 49.04 dB, the unity gain-bandwidth is 3.32 kHz, phase margin is 71.96 degree and power consumption is 53.3 nW. With CDB technique, the open loop gain is 53.54 dB, the unity gain-bandwidth is 19 kHz, phase margin is 50 degree and power consumption is 55.79 nW. DTMOS technique provides high open loop gain, CDB technique provides high unity gain-bandwidth and bulk-driven technique provides better phase margin. Also DTMOS technique has less input-referred noise than the other methods.

In the current paper, linear Digital Radio Frequency Memory (DRFM) is tested to steal Velocity Range Gate for use in electronic war. DRFM output signal steal both of the interval and velocity gate. This output signal spectrum has two important characteristics that, we use them in this paper. First, the central frequency shift is smaller and measurable than the central frequency of input signal. Second, the presence of harmonics with small amplitude being around the central frequency of the data shift. The main factor of the spectrum characteristics is the discrete nature of DRFM. We investigated the development of the states to predict the central frequency shift and harmonics location as a function of radar and DRFM parameters. When electronic war engineers could affect the system performance, these spectrum characteristics are taken attention. The analyzers of signal by these spectrum characteristics can evaluate electronic war systems better.

International Mobile Telcommunications-Advanced (IMT-Advanced) or alternatively 4th Generation (4G) Cellular Systems are mobile systems that extend and improve upon the capabilities of the IMT-2000 family of standards. Such systems are expected to provide users with access to a variety of advanced IP-based services and applications, supported by mobile and fixed broadband networks which are predominantly packet-based.4G networks can support a wide range of data rates with different quality of services requirements. Proportional to user mobility conditions in multiuser environments. WiMax embodies the IEEE 802.16 family of standards that provision wireless broadband access. with the IEEE 802.16e – 2005 or IEEE 802.16m mobility amendement, WiMax promise to address the ever increasing demand for mobile high speed Wireless data in forth – generation (4G) network. It provides wireless broadband and IP connectivity for the “first-mile to last mile” connection. In this paper we proposed a solution for designing 4G Networks by mobile wimax technology in urban with an intelligent Medium Access Control (MAC) that adapts with the Physical layer (PHY) to provides requirements 4G. In our scheme we present 24 scenario with different parameters. The performance of proposed scheme is evaluate by simulation using Opnet.

In this paper, analysis of a linearized Travelling Wave Tube (TWT) under the digital modulation schemes is presented. The pre-distortion linearizer circuit based on the schottky diodes and circulator is used to compensate nonlinear behavior of the TWT amplifier in the noisy channel. The Quadrature Amplitude Modulation (QAM) is utilized and applied before linearized TWTA in order to capture results. The data passing through the linearized TWTA is analyzed by using Advanced Design System (ADS). Constellation and eye diagrams are obtained from a telecommunication link. In addition, Bit-Error-Rate (BER) performance of the system is evaluated using Monte Carlo estimation for three different values of Input-Back-Off (IBO). Finally, it is shown that the system performance is improved considerably by applying the proposed signal pre-distortion linearizer base circulator.

In this paper a novel 1-bit full adder using hybrid-CMOS logic style is proposed. Hybrid-CMOS design style utilizes various CMOS logic style circuits to build new full adder with desired performance. The new proposed full adder is based on differential cascode voltage switch logic (DCVSL) XOR-XNOR gate which generate full-swing outputs. The complementary pass-transistor logic (CPL) is used to have minimum propagation delay and stability against noise in Sum signal. Also the transmission-gate logic (TG) is used to have high speed and full-swing in Cout signal. The circuit that consists of 16 transistors is simulated with HSPICE in 0.18 μm CMOS process by varying supply voltages from 1 V to 1.8 V with 0.2 V steps. The simulation results show that the proposed circuit has less power consumption and is faster in comparison to other circuits.