Design of an integrated phase frequency detector with optimal power consumption and delay by using particle swarm optimization algorithm

here is a growing interest in the optimal design of the phase locked loops، because these circuits are widely used in communication and electronic circuits. Undoubtedly the most important objectives in designing PLLs (phase locked loops) are low power consumption and low delay. In this paper، the process of designing and the optimization of PFD (one of the main part in PLLs) are proposed by using particle swarm optimization (PSO) algorithm. In the proposed method، instead of carrying out the frequent experiments and simulations based on trial and error to achieve the desired parameters of the phase frequency detector، effective variables are sent to the PSO algorithm and optimization process is done by this algorithm. The results show a remarkable ability of this heuristic method to find transistors sizing for optimal power consumption and delay.