CMOS Low-Dropout Voltage Regulator with Controlled Pass Transistor

This paper presents a low quiescent current low-dropout voltage regulator (LDO) with controlled pass transistor which can work either with on-chip or off-chip output capacitor. The pass transistor of the proposed LDO has lower width in low load condition and has higher width for moderate to heavy load current and the LDO topology transforms between a two-stage structure in low load current and a three-stage one in moderate to high load current. The proposed LDO topology is designed and simulated in HSPICE in a 0.35 µm CMOS process to provide a 2.8 V output voltage for a 3 V input voltage and is capable to deliver a stable output current in the range of 0-100 mA to the load with a 100 pF on-chip output capacitor while its quiescent current is only 7.5 µA. Without using the adaptively-controlled pass transistor, the maximum output variations of the LDO to the 0-100 mA load transient is 540 mV and its settling time is 11 µs, while using this technique decreases the output voltage variations and settling time to 280 mV and 6.5 µs, respectively.