Design of a Fault Tolerance FPGA-Based AES Encryption Engine

AES encryption algorithm (Rijndael) is one of the most common standard encryption algorithms. However, the major problem is the difference between encryption and decryption algorithms, and how to implement the algorithm on FPGAs. However, due to the sensitivity of the encryption and decryption operations, error-free output without delay is required which means the increased reliability and availability. In this paper, a brief review on Rayndal algorithm and the used redundancy technique will be discussed. Then, different implementation techniques are presented and the benefits of hardware implementation is discussed. Moreover, a new model for implementation the algorithm on the FPGA (including the encryption and decryption) is provided. This model is efficient in area and throughput. By pipelining, we achieve these goals and results. The synthesis results of the proposed encoding and decoding show good performance and efficiency validity of the proposed approach. Finally, as simulation results justify, the proposed model enhances the reliability, availability, performance, speed and data security.