Design of Delay locked loop for Wireless Receivers to Use in High Frequency Applications

In this paper, a new approach using gradient optimization algorithm for delay locked loop (DLL) is provided. Among the salient features of this structure, the proposed DLL can be quickly locked and can be used as a high-frequency circuit. In this novel architecture a digital signal processor (DSP) is used instead of phase detector, charge pump and loop filter. In digital transmitters to select kind of modulation, coding, decoding and…a DSP is used. Therefore, this DSP can be used in the proposed structure too. The proposed digital DLL has lower complexity than conventional analog DLLs. The structure is simulated using MATLAB for Bluetooth application. Five delay cells are used in the proposed digital DLL to generate 2.4GHz output frequency from 480MHz input frequency. The simulations confirm the high accuracy and speed of proposed digital DLL.