مجله مهندسی برق و الکترونیک ایران
سال بیست و یکم شماره 1 (بهار 1403)

The increasing growth of processing data size in digital systems has increased the number of connections between processing systems, which requires a lot of space to establish communication with other processing systems. The design and implementation of multi value level processing systems reduce the size of processing data. On the other hand, the important issue in the implementation of multi-level processing systems is problems and complications of design. The use of substitute transistors such as nano-carbon tube field effect transistors instead of metal oxide semiconductor field effect transistors while reducing design problems in nano dimensions is functionally more suitable than metal oxide semiconductor field effect transistors. In this article, a report on the implementation of a multi inputs full ternary comparator based on carbon nanotube field effect transistor technology is presented. The implementation report of the one digit and two-digit ternary comparator at the transistor level has been done in this article, and the implementation method of the multi-input ternary comparator has also been presented. The simulation results in the HSPICE software environment show that the power consumption of the proposed comparator is 0.55 µW and the propagation delay time is 70 ps. In addition, the proposed comparator has been implemented based on 32 nm carbon nanotube field effect transistors technology.

Today, CMOS technology circuits are faced with basic challenges in parameters such as speed, frequency, and power consumption due to the impossibility of further reducing the dimensions. In this regard, one of the solutions proposed by the researchers is to introduce alternatives to this technology, among which we can mention the quantum-dot cellular automata technology (QCA). A lot of research has been done to design digital circuits in QCA technology. Since the full adder circuit is one of the integral parts of a arithmetic and logic unit, it is one of the circuits that is of interest to designers familiar with QCA technology. Therefore, in this paper, the design of a new full adder is prioritized. In this article, using a three-input XOR gate and a three-input majority gate, a full adder is designed that has 35 cells, an occupied area of 0.03 micrometer square and 2 delay clock regions. The proposed full adder has made good improvements in terms of the features compared to the previous designs. To confirm the function of the proposed structure, simulation has been done by QCADesigner software.

In this paper, for the first time, the distributed potentials in the front and back gate of Ultra-Thin-Body (UTB) Double-Insulating (DI) Silicon-on-Diamond (SOD) MOSFET are computed. The back gate and front gate threshold voltages of the device are computed. Using parabolic potential distribution in the body of the device, the poison’s equation is solved. Promising results are obtained for front and back gate threshold voltages comparing with the 22nm UTB DI SOD and the device simulation results. The gate insulator thickness, the silicon film thickness, the insulator 1 and 2 thicknesses are varied and the front and back gate threshold voltages are computed while comparing the device simulation results. Lower than 20 mV estimation of the threshold voltages using the analytical computations, dictates promising results incorporating the device capacitive model. The Analytical findings are encouraging for threshold voltage estimation of UTB DI SOD MOSFETs.

Today, the advancement of technology and the miniaturization of devices and chips in electronic apparatuses along with the demand for their portability and their operation for a longer period of time, have put great challenges in front of the designers of analog integrated circuits. Current mirror is an important component in the design of analog circuits and one of the most widely used circuits in which the power consumption is influenced by the supply voltage. Therefore, it is necessary to develop structures of low-voltage and low-power current mirrors to meet the requirements of CMOS design. In this paper, a low-voltage low-power current mirror has been designed using cascode structure in combination with quasi-floating gate MOSFET technique, and two stages gain boosting amplifiers have been used to increase its output resistance. For this purpose, SPICE simulation environment has been used considering TSMC 180 nm CMOS technology. The proposed current mirror employs a supply voltage of ±0.3V and its input and output resistances are 48 Ω and 432 MΩ, respectively, and its bandwidth is 244.2 MHz. The main advance of the proposed current mirror in comparison to similar works is its low power consumption of 14.03 µw.

In this paper, for the first time, a capacitive model near threshold voltage of Ultra-Thin-Body (UTB) Double-Insulating (DI) Silicon-on-Diamond (SOD) MOSFET is extracted.  The model is applicable in computations of front- and back-gate threshold voltage of 22 nm UTB DI SOD MOSFET for low drain voltages. The transistor has a second insulating layer on top of first insulating layer of conventional SOD MOSFET which partially covers the diamond layer. The device simulation results of the front- and back-gate threshold voltages and the extracted model threshold voltages in terms of gate oxide thickness, silicon film layer thickness, first and second insulating layer thicknesses are compared.  The comparison with the model computed results and the device simulation outcomes are promising. The model physical findings present insight on the device parameters that directly influence the threshold voltages.

In this paper, the effects of size, material, position and period of metal nanowires on the performance of thin film solar cells have been analyzed. For this purpose, full-wave simulations of the solar cells with gold, silver and nickel nanowires with different radii, periods, and positions have been used. The simulation results show that the best performance of the thin film solar cell has been realized when the gold nanowires with a radius of 70 nm and the period of 425 nm have been positioned on the top surface of the active layer. The optimum values of the efficiency and short circuit current density have been calculated as 22.22% and 22 (mA/cm2), respectively.

In this paper, we have analytically investigated the effects of temperature and electric field perpendicular to the silicene surface on the transverse electric wave propagation range in the frequency range of 1 to 30 THz. Unlike graphene, the atomic structure of a silicene composite is not flat, which makes the surface conductivity of silicene, in addition to the Fermi level, adjustable with an electric field perpendicular to the silicene surface. This property allows silicene to emit transverse electric waves over a wider range than graphene. According to the simulation results based on Kubo equations, per vertical electric field of 100 mV/Å, the propagation bandwidth of TE waves at temperatures of 5 K, 100 K, 200 K and 300 K are equal to 9.2 THz, THz 8, 1.3 THz and 0.9 THz, respectively. By increasing the vertical electric field to 200 mV/Å, the bandwidth for these temperatures will be 20.7 THz, 20.6 THz, 16.7 THz and 11.7 THz, respectively. In the vertical electric field to 300 mV/Å, these values ​​are 29 THz, 28.8 THz, 26.4 THz and 21.8 THz, respectively. The confinement length of TE waves in the propagation ranges has also been obtained, which has increased the trapping length with increasing temperature.

Flexible electronic devices, as an emerging field of research, has received extensive attention in recent literature. Given, the progress, developments and growing demands in this field of research, wide-range research has been carried out on flexible materials in academic as well as industry. Due to the replacement of the conventional rigid devices with their flexible and stretchable counterparts, widespread high-quality research is needed to make this transition feasible. In particular reliability is of paramount importance in real-world applications and is needed to be addressed in the relevant literature. In the literature, mostly materials and methods have been reported. In this manuscript, we have summarized recent progress in the field of stretchable and flexible electronics. Key characterization parameters including reliability, hysteresis and linearity have been discussed. Nonetheless, for being adapted successfully into real-world applications, mass production techniques in this field of research has been presented.

This paper presents a cascaded 2-2 reconfigurable sigma-delta modulator that can handle GSM and WCDMA standards. In GSM mode, only the first stage (2nd order Σ-Δ ADC) is turned on to achieve 83dB dynamic range with oversampling ratio of 160 for a bandwidth of 200 KHz ; in WCDMA mode a 2-2 cascaded structure (4th order) is turned on with 1-bit in both stage to achieve 65 dB dynamic range with oversampling ratio of 16 for a bandwidth of 2 MHz .The results show that power consumption of proposed modulator is lower than other counterparts. Modulator are simulated by Cadence software utilizing 180 nm TSMC technology and operates at 1.8 supply voltage.

A DC-DC converter with a quasi-active switched-inductor structure for renewable energy systems is introduced in this paper. In the presented structure, the switched inductor method is integrated with the coupled inductor. The proposed converter consists of four capacitors, four diodes, two active switches and two coupled inductors derived from the switched inductor network and can be integrated into one magnetic core. The primary side of the coupled inductors are charged/discharged in parallel/series by the input source. Two sets of diode-capacitor, in addition to increasing the voltage conversion ratio, reduces the voltage jump caused by the leakage inductor, as a result, the voltage stress on the power switches is limited. Therefore, two switches with low conduction resistance can be used to reduce conduction losses, thus increasing efficiency. Also, two diodes do not have the problem of reverse recovery due to turn off naturally, the reverse recovery problem of the output diode is also reduced by the leakage inductor. Operating principles and steady state analysis are discussed in detail. Then, the performance of the proposed converter is compared with existing converters. Finally, a laboratory prototype was created and experimental results are presented to verify its performance.

In this paper, low-noise amplifier Ultra-Wideband is presented. The proposed LNA uses shunt peaking and series peaking technique to extend the bandwidth. A current-reused architecture is employed to decrease the power consumption. Simulated in 180nm RF-TSMC CMOS technology, the proposed Ultra-Wideband LNA achieves a maximum power gain of 15.3 dB, NF of 5.74-5.88 dB, 3 dB bandwidth from 1.16 GHz to 10.34 GHz, While consuming 11.7 mW power (including buffer) from 1.8 V supply.

The field of embedded systems for cryptographic applications is constantly growing and new methods and applications are emerging. In this paper, high-speed hardware architectures of point multiplication based on the Montgomery ladder algorithm for binary Edwards and generalized Hessian curves in Gaussian normal basis are presented. Computations of the point addition and point doubling in the proposed architecture are concurrently performed by pipelined digit-serial finite field multipliers. The multipliers in the parallel form are scheduled for the lower number of clock cycles compared to other works.  The structure of the proposed digit-serial Gaussian normal basis multiplier is constructed based on regular and low-cost modules of exponentiation by powers of two and multiplication by normal elements. Therefore, the structures are area efficient and have low critical path delay. Implementation results of the proposed architectures on Virtex-5 XC5VLX110 FPGA show that execution time of the point multiplication for binary Edwards and generalized Hessian curves over GF(2163) and GF(2233) are 8.62 µs and 11.03 µs, respectively. The results show improvements in terms of execution time and efficiency compared to other's related works. For example, for binary Edwards curves over GF(2163) (on Virtex-4 XC4VLX110 FPGA) the proposed design can reduce hardware resource utilization, execution time, and efficiency by up to 17%, 30%, and 42%, respectively, compared with other the best previous architecture.

This paper is to provide a model for effective management of electronic banking in the ease of transmitting information using data mining techniques. The proposed model of the research is developed according to the variable factors such as data validity, internal control, system access, security, technology in Iranian banks. The stages of this study are conducted in Clementine software using 300 samples gathered from customer’s data and transactions in two major branches of the Tejarat Bank located in Tajrish and Sadeghieh (Tehran), in the 1398. The most important results of the present study are that the main predictors of the model, namely, the classification of sensitive information (D5), the existence of antivirus software (D4), network penetration testing (D3), provide a more accurate analysis and predict effective management of electronic banking in the ease of transmitting information. Finally, our achieved results show that the predictors could predict effective management of electronic banking in the ease of transmitting information using data mining techniques with 72.7% accuracy.

Nowadays, high-entropy alloys (HEAs) are a popular domain for researchers which is improved performance by using machine learning (ML). HEAs are formed at least five main elements with close or equal size which is depend on their size and type of elements to extend physical and mechanical features. The ML approach has many applications in various fields. Social network analysis (SNA) is one of the ML tools that is used graph theory. Each graph consists of a number of nodes and edges that each node has its own descriptors. The studies done so far has not used the high-entropy alloys network dataset based on the similarity of content and structural features of each compound. In this paper, a new method is proposed that generalized SNA tools to metallurgical and materials engineering. The proposed method is investigated the HEAs descriptors, in which HEAs descriptors similarity are calculated and the HEAs interaction network is created. The groups have been extracted by Louvain algorithm which each group called cluster. The clusters have alloys with similar properties. The experimental results shown high quality clusters that will be effective in predicting the compounds functionality and discovering new compounds and descriptors. The modularity criterion indicates the quality of the clusters, is about 0.713.

Air travel has significantly grown as a fast and safe means of transportation. Therefore, creating a smooth air traffic and proper flight scheduling for safe landings with minimal time changes is necessary to avoid wasting time and money. In most studies, the aircraft landing scheduling problem has been considered a static issue. However, this challenge has a dynamic nature in real-world problems. One of the optimizing approaches in this scope is swarm intelligence optimization algorithms, which are simple and highly capable in solving optimization problems. Among these algorithms, Spider-Monkey optimization algorithm is more efficient than traditional algorithms by using few parameters, maintaining search history, controlling searches, and grouping members of the population if needed. In this study, an active scheduling method for aircraft landing scheduling using Spider-Monkey optimization algorithm and genetic algorithm has been presented. The proposed method is examined by some datasets of single and multi-runways (single and multi-objective aircraft landing). The achieved results show an improvement in flight schedules and reduced costs.