Low-Power Register File Design in 90nm CMOS Technology

The main portion of the power consumption in high speed register files is related to read out paths which are implemented using the dynamic circuits. For this reason, a new dynamic circuit technique is proposed in this paper to reduce the power consumption of the register files without significant speed and noise immunity degradation. In the proposed dynamic circuit, the pull down network is partitioned to the some smaller pull down networks to increase the circuit performance. Moreover, pull-down networks are precharged using NMOS transistors to reduce the voltage swing and hence decrease the power consumption. A 64-word x 32-bit 2-read, 1-write ported register file is implemented using the proposed circuit technique. Simulation of register files are performed using HSPICE simulator in low-Vth 90-nm CMOS technology model. Simulation results demonstrate 37% and 36% reduction in power and delay respectively at the same noise immunity compared to the conventional register file.