Performance and Reliability Improvement on 2D-NOC Based on Reducing the Number of Passing Links

Network on-chip is a communication subsystem within an integrated circuit that provides communication between processors in the on-chip system. There are several different ways to get from one node to another. Therefore, there must be a routing algorithm to find the route to the destination. This paper presents an algorithm based on the reduction of the passing path to reach a packet from origin to destination which is able to increase the reliability, reduce latency, power consumption and increase network efficiency on the chip. And this is when most of the fault-tolerant networks presented in this field increase parameters such as delay, power consumption and circuit complexity in order to achieve higher reliability. The proposed method improves network performance with minimal hardware changes and circuit complexity. The path passed by the packet is reduced to reach the destination, which means passing through fewer links and routers and less chance of encountering faulty links and routers and increasing network reliability. Also, passing fewer links and routers will reduce network latency and power consumption.