Improved of Linearity Performance With low Common-mode Voltage Variations for Non-binary Successive Approximation ADC With a Monotonic Switching method

In this paper, a fully differential successive approximation A/D converter is presented using the extended non-binary search algorithm with an accuracy of 10-bits, 11 comparison steps, and the sampling rate of 4.17MS/s which is suitable for low-power applications because it does not require to be calibration. In the non-binary search algorithm, there are overlaps between the search rang, that allow comparison decision errors to be digitally corrected. To improve the linear behavior of the proposed structure, a capacitive array D/A converter with non-binary weight is implemented, and the sampling frequency is increased compared to the conventional successive approximation converter through proper selection of non-binary capacitances of the capacitive array. The proposed structure operates based on monotonic switching logic. This switching method reduces the power consumption of DAC compared to conventional switching. The proposed structure is designed using 180nm CMOS technology and the simulation results show that for a supply voltage of 1.8V, signal to noise and distortion ratio (SNDR) is 61.35dB, power consumption is 78.14µW, and figure of merit is 19.57(fj/Conv.step).