New Capacitance Switching Technique with Low Sensitivity to Common-Mode Voltage Variations for Differential SAR ADCs

In this paper, while describing the operation of the ADC SAR, we examine the blocks that make up this converter and the share of each of the circuits is in total power consumption and tried to reduce the power consumption. Since the DAC and comparator respectively have the highest power consumption in this type of converter, most designers pay attention to the two sides to reduce power consumption. DAC design is more important from these two circuits, so an analog to digital converter with the fully differential is proposed with a proposed switching method to reduce the power consumption of the DAC. In this converter, the energy consumed DAC has fallen by 86% compared to conventional structure and has decreased by 24.65%compared to the monotonic structure. Due to the performance of the DAC complement switching of the upper and lower half-circuits, caused the voltage variations of the common-mode inputs of the comparator to be constant from step two to the next, and this improves the constant of the voltage variation of the common mode of our circuit deflection Which is the benefits from this proposed method. All simulation in the 0.18 μm CMOS technology with 1.8-V power supply is done.