Novel Design of Multiple-Valued Interconnection networks to improve processing speedin hardware secuirity

In this research we present the novel designs for high speed interconnection networks. Despite classical interconnection networks, in these design two and three processing elements can communicate in the same time on the same line. The designs comprise simple elements like MOSCAPs. It enjoys very high speed and consumes low chip area. Even if in the first glance it seems complicated to be realized in real VLSI but using MOSCAPs results in simple realization of the overall circuit as well as achieving very high speed. The simulation results confirm that the voltage mode MVL interconnection network has achieved simultaneous data transfer, and the static power consumption and delay has been improved. According to the subthreshold characteristics of 180 nm technology compare to 65nm, the mean delay of the proposed structures in 180 nm is lower than 65 nm.The results show that the delay and power consumption in interconnection networks with two processing elements using wires compared to DC-2 approach in 65 nm technology are decreased respectively from 500.0126×10-6 to 159.9667 ×10-12 and 3.422×10-9 to 178.1493×10-15 . Due to the capability of simultaneous communication by defined voltage levels, , there is significant improvement on the performance characteristics, such as transmission delay and power consumption.The results of this study can be used to enhance the security of information and communication technology systems, organization and business equipment of future generations of security systems.