One-bit Full Adder with Low Delay and Low Cell Count in the Emerging Technology of Quantum-Dot Cellular Automata

Today, CMOS technology circuits are faced with basic challenges in parameters such as speed, frequency, and power consumption due to the impossibility of further reducing the dimensions. In this regard, one of the solutions proposed by the researchers is to introduce alternatives to this technology, among which we can mention the quantum-dot cellular automata technology (QCA). A lot of research has been done to design digital circuits in QCA technology. Since the full adder circuit is one of the integral parts of a arithmetic and logic unit, it is one of the circuits that is of interest to designers familiar with QCA technology. Therefore, in this paper, the design of a new full adder is prioritized. In this article, using a three-input XOR gate and a three-input majority gate, a full adder is designed that has 35 cells, an occupied area of 0.03 micrometer square and 2 delay clock regions. The proposed full adder has made good improvements in terms of the features compared to the previous designs. To confirm the function of the proposed structure, simulation has been done by QCADesigner software.