International Journal of Industrial Electronics, Control and Optimization
Volume:7 Issue: 1, Winter 2024

This study examines stability improvement of the power system which includes Double Feed Induction Generators (DFIGs) and Static Series Synchronous Compensator (SSSC). The proposed nonlinear controller is designed based on the terminal sliding mode control theory. A sliding mode observer is also developed to remove the need to access the information of all the state variables. The final closed-loop of the power system modeling is robust against parameter variations and uncertainties. The limitations of the control signals in the process of controller design are also considered. The application of such a method increases the stability margins and results in higher robustness degrees. A comparison with other nonlinear approaches such as back-stepping and feedback linearization approaches is carried out. The results show the faster and more reliable convergence rate of the power system-controlled trajectories to reach back to the equilibrium point after occurring a sudden fault. The results are obtained by performing a simulation on the standard 39-Bus, 10 machines NEW ENGLAND power system.

The modular multilevel converter (MMC) is a favored topology in the industry, but its reliability is at risk with an increase in the number of sub-modules (SMs) due to a rise in switching components. The essential need for maintaining capacitor voltage balance in each arm leads to increased complexity and cost, as numerous voltage sensors are required. This study introduces an innovative approach to minimize the number of voltage sensors by employing an enhanced algorithm for open-circuit fault detection in switches. The proposed scheme organizes each arm into groups, each containing two SMs and one voltage sensor, aiming to reduce the overall sensor count. A novel fault detection mechanism is presented, identifying open-circuit faults by comparing group output voltages in healthy and defective conditions. The capacitor voltage estimation algorithm in the sensor reduction scheme is noted for its simplicity compared to other methods. The effectiveness of these methods is validated through simulations and experimental implementations across diverse scenarios, affirming their reliability.

This article presents development and implementation of an integer N-type Phase Locked Loop (PLL) module with two output frequencies of 1 and 4 GHz, each having a phase noise better than -110dBC/Hz@10k. The structure has 0 and 10dBm power levels at 1 and 4GHz output frequencies, respectively. Having two different outputs of 1 and 4 GHz at once, in addition to the 1.1 and 4.4GHz realized by the capability included in this design in which two additional outputs can be achieved by using the pins A0 to A4 and altering their status, makes this structure a good candidate for mass production. A two-step frequency division is employed in this work. The first step is realized using the frequency divider of order 4, and the second step is implemented inside the HMC440 IC, including a PFD and a counter. Compared to typical methods, this method presents a clean output by suppressing the spurs meant to be manifested using a single-step frequency division. This PLL is constructed in discrete and modular modes and employed in transceivers’ up-converter and down-converter blocks, Satellite communications, Cable TV links (CATV), Local Area Networks (LAN), Global Positioning Systems (GPS), test equipment, digital radios, military and commercial communications. For a specific example, the 4GHz frequency is used to up-converte or down-converte the received signals, and the 1-GHz frequency is usually used for the synthesizer module clock frequency. Advanced Design System (ADS) was used in the design, and OrCAD was used in the schematic design of the PLL module.

In this paper, we design a lightweight and modified random key generation for PRESENT block cipher which is applicable in the encryption of the digital signals. In the block ciphers, the master key is used directly in the encryption process for the data (plaintext). But in this work, a master key (initial key) is used to derive the new random master keys (random session keys) and use these keys for the encryption process. The use of random keys will overcome the brute force attack that can be applied to the PRESENT cipher. The random session keys generated will produce different ciphertexts for the same plaintext for every session. In this approach, we take advantage of the block cipher to produce random keys. The PRESENT cipher is shared in both random key generation and encryption process. Therefore, the proposed structure has both random key generation and data encryption in a unified circuit. This property reduces hardware resources. The implementation results, in 180 nm CMOS technologies, show the proposed structure is comparable in terms of area and delay with other works.

In this article, time-varying chaotic systems with uncertainties, including external disturbances, are considered, and sliding mode control (SMC) is used to control such systems. To control these systems, an autonomous differential equation is first introduced. Then, based on this differential equation, a sliding surface is defined to control this chaotic system. This kind of controller is remarkable in that it removes the effects of disturbances, whether bounded or unbounded. Therefore, the system is known to be fixed-time stable. where the trajectories of this chaotic system are not placed on the sliding surface, we have created creative controllers to place the trajectories on the sliding surface in finite time. Theoretical investigations show that such chaotic systems can be made fixed-time stable by applying the controls proposed in this study. Based on the findings of this study, the controllers are designed to eliminate all disturbances, whether bounded or unbounded. the results be said to apply chaotic, time-dependent, and time-independent systems. To further consolidate the results obtained in this article, two examples, namely the time-dependent system of the Gyro and the time-independent system of the Liu, are investigated, and the results were compared with previous works by other researchers.

In recent years, to increase the number of pulses in 12-pulse autotransformer rectifiers (12-PARs) and reduce the input current total harmonic distortion (IC-THD), without increasing the cost and complexity, the technique of pulse multiplication circuit has been proposed. With this approach in this paper, to upgrade the rectifier structure from 12 pulses to 36 pulses, an auxiliary pulse tripling circuit (APTC) with a very small kilovolt ampere rate (a kilovolt ampere equal to 1.34% of the rated load power) is presented. The proposed APTC consists of an unconventional interphase transformer (UIPT) with two diodes in the primary winding and a single-phase diode bridge rectifier connected to the secondary winding. Also, the 12-phase autotransformer used in the proposed structure is based on a polygon connection with a very low kilovolt-ampere rate. As a result, the total kilovolt-ampere rate of the proposed 36-pulse autotransformer rectifier (36-PAR) is about 24% of the rated load power, which is much less compared to similar structures. Also, according to the simulation results, the IC-THD in the proposed rectifier is less than 3%.

In this paper, a method is presented to design and implement ultra-wideband phase shifters, in frequency ranges higher than 10 GHz, with fractional bandwidth near a hundred percent. The phase shifter is constructed from microstrip transmission lines and short circuit stubs. In comparison with conventional phase shifters which are composed of microstrip coupled lines and multilayer structures, the proposed phase shifter has advantages from the implementation and fabrication viewpoint. The design and optimization method is in such a way that arbitrary phase shift, source and load impedances may be considered in the design. To optimize the circuit dimension, a computer code is written, and two design examples are considered. The computer code is based on closed form equations for microstrip transmission lines and available circuit models for it and utilizes microwave network equations. Its results are then improved with electromagnetic full-wave packages to consider the parasitic effects of microstrip T-junctions. Two design cases are included, in the first design, the case of a 45 degrees phase shifter with a standard 50 ohms source and load impedances is investigated. In the second design case, the case of a 90 degrees phase shifter with 50 ohms input impedances and 75 ohm non-standard output impedances is considered. By observing the full-wave simulation results as well as the fabrication and measurement results in these examples, it is clear that the design goals are highly satisfied by this method.