Soft Error Tolerant Design of Combinational Circuits using a Local Logic Substitution Scheme

In this paper, a re-synthesize technique based on the local logical replacement in order to reduce the soft error rate of combinational circuits is proposed. The proposed method provides an innovative technique to increase the logical masking probability considering the area overhead. In this technique, at first, using an extended Quine-McCluskey (QM) method, the sub-circuits be extracted from the main circuit; while, different implementation carried out on the extracted sub-circuits. In order to choose the best alternative among the different implementations of a sub-circuit with the lowest soft error rate, a new parameter named as Global Failure Probability (GFP) is introduced. Experimental results on some ISCAS’85 benchmarks show that, on average, a probability of circuit failure reduction of 17. 75% is achieved compared to the original circuit. The average area overhead is 5. 39% of the original circuit.