Write Error Rate Reduction Based on Thermal Effect and Dual-Vdd

Write Error (WER) is one of the most drawbacks of STT-MRAM based memories. This problem usually occurred because of thermal instability and process variation. Although some methods have been proposed for WER reduction, they often did not consider the thermal effect of MTJ and had significant overhead. Therefore, proposing a new method in a lower layer of abstraction with the minimum penalty is essential. In this regard, a write driver core has been proposed, which uses two distinct ways according to the state of writing data based on the thermal feature of MTJ cell and by Dual-Vdd method. Simulation results show 11.38% write latency reduction without area and power penalty.