Improvement of Single-Phase Dynamic-Latched Comparator

In this paper, single-phase dynamic comparator was improved based on adding a clocked NMOS auxiliary latch at its output and two clocked NMOS transistors at its internal nodes. Using clocked NMOS latch and transistors increased the speed of comparator, without increasing the loading effect and kick-back noise on its previous and next stages. The advantage of the proposed comparator rather than the conventional comparator was higher speed with precence same power dissipations. To demonstrate the mention specifications, proposed and conventional comparators were analyzed and simulated at 2-GS/s sampling rate in 0.18-μm CMOS process. In this case, the outputs of proposed comparator were determined almost 18-ps (%9) faster than the outputs of conventional comparator. Also, to compare the performances of proposed and conventional comparators in flash ADCs, two 4-bits flash ADCs, using proposed and conventional comparators in their comparison chains blocks, were designed and simulated at 2-GS/s. In this case, the FOM of ADCs with the proposed and conventional comparators at nyquist rate input frequency achieved 0.61-pJ/conv.step and 0.72-pJ/conv.step, respectively. Corresponding, the ENOB of ADCs achieved 3.74-Bit and 3.45-Bit, respectively. In addition, the power dissipations of comparators array of ADCs with proposed and conventional comparators were 4.23-mW and 4.09-mW, respectively. Also, the power dissipations of two flash ADCs, without the power dissipations of their comparators array, were 11.70-mW and 12.03-mW, respectively.