Design and optimization of an Approximate Full-adder Based on CNTFETs and its application in image processing

Novel digital circuit design methods are vital due to the significant increase in data that requires fast processors. No doubt, power consumption is an essential factor in electronic devices. Hence, the design of low-power, area-efficient, and high-performance circuits is crucial. Approximate computing as a promising method for designing efficient circuits in addition to applying CNTFETs can be an excellent solution for the concerns mentioned above. In this article, according to the full adder’s importance in DSP processors, a new approximate full adder based on 32nm Stanford CNTFET model is proposed and optimized in terms of power consumption, delay, PDP, and the number of transistors. HSPICE is applied to compare this new design with state-of-art articles. The simulation results indicate that the proposed design has not only the least delay but also shows an 87% improvement in PDP achieved. Various simulations applying different load capacitors, supply voltages, and process variations demonstrate the acceptable functionality of proposed approximate full-adder in different situations. Image addition simulation using MATLAB is applied to assess the performance of the proposed design in a real error-resilient application.