Designing a Low-Noise Delay Locked Loop using Concurrent Charge-Pump

In this paper, a new circuit is proposed for charge pump for using in delay locked loop, and then simulated in ADS software in 0.18 μm TSMC CMOSRF technology with 1.8V in transistor level. By using DLL a precise synchronization can be performed through internal and external clocks. In this paper, based on introduced charge pump current mismatching can be solved and so the jitter will be decreased. Finally, 3.7psec effective jitter in 920MHz for DLL is accrued. In this loop while UP and DN in each duty cycle are proportional to dead zone, not considerable current is flow on the output of CP. Because the UP and DN signals are in current source and by switching each one, probability of following the current to the output will be provided. However, prevents current transition to other switch if turned on.