High-speed Hardware Implementations of Point Multiplication for Binary Edwards and Generalized Hessian Curves

The field of embedded systems for cryptographic applications is constantly growing and new methods and applications are emerging. In this paper, high-speed hardware architectures of point multiplication based on the Montgomery ladder algorithm for binary Edwards and generalized Hessian curves in Gaussian normal basis are presented. Computations of the point addition and point doubling in the proposed architecture are concurrently performed by pipelined digit-serial finite field multipliers. The multipliers in the parallel form are scheduled for the lower number of clock cycles compared to other works.  The structure of the proposed digit-serial Gaussian normal basis multiplier is constructed based on regular and low-cost modules of exponentiation by powers of two and multiplication by normal elements. Therefore, the structures are area efficient and have low critical path delay. Implementation results of the proposed architectures on Virtex-5 XC5VLX110 FPGA show that execution time of the point multiplication for binary Edwards and generalized Hessian curves over GF(2163) and GF(2233) are 8.62 µs and 11.03 µs, respectively. The results show improvements in terms of execution time and efficiency compared to other's related works. For example, for binary Edwards curves over GF(2163) (on Virtex-4 XC4VLX110 FPGA) the proposed design can reduce hardware resource utilization, execution time, and efficiency by up to 17%, 30%, and 42%, respectively, compared with other the best previous architecture.