مجله مهندسی برق و الکترونیک ایران
سال هجدهم شماره 1 (بهار 1400)

One of the main problems of field effect diode (FED) is the increasing of its turn-off current as the channel length decreases. Thus, in this paper, a new structure is presented which decreases the injection of extra carriers to the channel and also increases the control of the gate over the channel by reducing the portion of channel shared with the source and drain regions and without the need for reservoirs. Using this technique and without the need for the reservoirs, the source and drain regions increase in size compared to the S-FED structure, and turn-on current is enhanced. Therefore, by comparing the proposed structure with S-FED, it is demonstrated that the important parameters such as Ion, Ion / Ioff ratio, Gate Delay, and EDP have been improved, and this structure can be a proper alternative to conventional structures.

The electrical properties and rectification behavior of the graphene self-switching diodes by side gates doping with nitrogen and boron atoms were investigated using density functional tight-binding method. The devices gates doping changes the electrical conductivity of the side gates and the semiconductor channel nanoribbons. As a result, the threshold voltage value under the forward bias is significantly reduced, so that in the boron and nitrogen doped 565 structures, this voltage is close to zero. Also, relative to the undoped structure, the electric current under the forward and reverse biases of the doped devices are increased and decreased, respectively. Among all the structures, the boron atoms doped 565 structure has the highest rectification ratio of 558.58 and also, the maximum current under the forward bias is related to this structure with the value of 8.56 μA.

This paper proposes the use of DTMOS transistors in a memristor-based ternary CAM (MTCAM) instead of MOSFET transistors. It also evaluates the effect of forward body biasing methods in DTMOS transistors on the performance of a MTCAM cell in write mode. These biasing methods are gate-to-body tying (called DT1), drain-to-body tying (called DT2), and gate-to-body tying with a voltage supply of 0.1 V (called DT3). The simulation results of DTMOS-based MTCAMs in comparison with a MOSFET-based MTCAM showed that the use of DT1 method enhances power dissipation and Power Delay Product (PDP) by 86% and 42%, respectively but increases the delay by 30%, the use of DT2 method enhances power dissipation and PDP by 87% and 60%, respectively but increases the delay by 20%, and the use of DT3 method enhances power dissipation and PDP by 89% and 74%, respectively but increases the delay by 14%. As a result, DT3-MTCAM has the least power and delay. Therefore, it is more suitable for low power applications. Simulations are performed in 40 MHz and 180 nm CMOS technology.

According to contact type, RF MEMS switches are generally classified into two categories: Capacitive switches and Metal-to-Metal ones. The capacitive switches are capable to tolerate a higher frequency range and more power than M-to-M switches. This paper presents a cantilever shunt capacitive RF MEMS switch with characteristics such as low trigger voltage, high capacitive ratio, short switching time and high isolation. In this switch, aluminum bridge is used because of its high Young’s modulus and low density which help reduction of switching time. Also aluminum has a good electrical conductivity which increases isolation. The proposed switch is designed on a Coplanar Waveguide line (CPW) with impedance of 50Ω. Also,  is used as dielectric layer. 24 holes have been placed on the bridge surface to reduce the squeeze film damping and to increase the switching speed. Actuation voltage is 5.2v and capacitive ratio (CR) is 231. RF analysis is done in HFSS Software. The results show the isolation level as -27dB, insertion loss as -0.2dB and return loss as -22dB at 17GHz. Also, the switching time is 32us.

In this paper, for the first time, the effect of the substrate doping of 22nm double-insulating UTBB silicon-on-insulator device on the switching performance and turn-on delay of the transistor is investigated. In UTBB devices, the substrate voltage is varied from positive to zero then negative voltages to trade-off transistor speed against the leakage current. Various circuit design procedures are followed to accomplish dynamic frequency-voltage scaling (DVFS). The switching delay from positive to negative substrate voltages are often considered negligible in comparison with typical 1 mS delay of the switching circuit itself. We show that the transistor switching delay is completely comparable with that of the switching circuit at the substrate doping of 1015 cm-3. Indeed, at this doping, the transistor delay is 1 mS and as the substrate doping increases to 1018 cm-3, the delay reduces to 0.03 nS. Therefore, the substrate doping directly influences the switching delay and output voltage settling time of the transistor and if ignored, will result in increased noise and degraded jitter performance.

The high-energy UV ray radiation on PIN Silicon photodiodes reduces the optimal parameters of these photodiodes. In this paper, by representing a model, we compare the effect of UV dose on the bright current in these two types of photodiodes and confirm the analytic relationships in order to simulate a model with the help of the Silvaco- Atlas software. In this model, Silicon photodiodes and Gallium Arsenide were investigated under the influence of 300nm UV source radiation in several reverse bias, and we arrived at a logical connection between the analytical and simulation results, and finally, in order to compare these two types of photodiodes, we have shown that the current of darkness in the photodiode has increased significantly with UV dose radiation. Also, the bright current in the Gallium Arsenide photodiodes is not much more than its Silicon model. This phenomenon indicates a higher sensitivity to Gallium Arsenide photodiodes.

With the advancement in technology and shrinkage of transistor sizes, especially in technologies below 90 nm, one of the biggest problems of the conventional CMOS circuits is the high static power consumption due to increased leakage current. Spintronic devices, like magnetic tunnel junction (MTJ), thanks to their low power consumption, non-volatility, compatibility with CMOS transistors, and the possibility of high density construction, are one of the alternative candidates for designing hybrid MTJ / CMOS circuits. In recent years, several magnetic memories have been designed and implemented using MTJs, these memories suffer from problems like high power consumption and low speed. In this paper, a new writing circuit for reducing the power consumption of the circuit and some modifications in the write circuits to reduce static power are proposed. Simulation results suggest that the proposed memories offer up to 97% lower static power consumption and up to 71% lower dynamic power consumption than previous counterparts.

In this paper, the performance of an optical modulator based on indium tin oxide is investigated at telecommunication wavelength for different accumulation thickness. The plan of metal-oxide-semiconductor is utilized to change the carrier concentration at indium tin oxide-hafnium oxide interface. An optical mode solver based finite element method has been used to calculate the basic parameters such as the insertion loss and extinction ratio. A typical model is presented for carrier concentration modeling of indium tin oxide. The simulation result shows a peak in insertion loss plot with value of 8.4 dB/μm. Also, the variation of ITO and HfO2 thicknesses have been investigated. The results show that by increasing the thicknesses, insertion loss and extinction ratio decrease. Furthermore, the effect of accumulation layer thickness of indium tin oxide is investigated on modulator performance.

In this paper, a plasmonic filter made of a split ring, two U-shaped structures and two straight waveguides is designed and investigated. In the proposed structure, the split ring and U-shaped structures are situated between straight waveguides. Simulations are done based on FDTD method. Split ring, U-shaped structures and straight waveguides are made of air in the silver background. In the proposed structure, by altering the split angle, transmitted power and resonance wavelengths can be changed and tuned. The structure can confine light to sub-wavelength dimensions (on the order of nm) which makes it appropriate for optical integrated circuits. By adjusting the structural parameters, transmission powers up to 90% can be obtained.

Quantum-dot cellular automata (QCA) technology is an alternative to overcoming the constraints of CMOS technology. In this paper, a new structure for D-type latch is presented in QCA technology with set and reset terminals. The proposed structure, despite having the set and reset terminals, has only 35 quantum cells, a delay equal to half a cycle of clocks and an occupied area of ​​39204 nm2. Then, this structure has been used to implement D-type flip-flops that are sensitive to the rising, falling, and both edges. For example, the proposed structure of the rising edge D-type flip-flop has a 55 quantum cells with a delay of 0.75 clock cycles and an occupied area of ​​61404 nm2. In order to prove the proposed circuit behavior in more complex circuits, these structures have been used in the form of phase-frequency detectors, frequency dividers, and counters. Simulation of power parameters has been done for proposed structures.

The purpose of this paper is to design a 64×64 bit low power, low delay and high speed Arithmetic Logic Unit (ALU). Arithmetic Logic Unit performs arithmetic operation like addition, multiplication. Adders play important role in ALU. For designing adder, the combination of carry lookahead adder and carry select adder, also add-one circuit have been used to achieve high speed and low area. In multiplier design, Booth algorithm and Wallace tree structure have been used. The proposed multiplier is based on Pipeline technique. In Wallace structure, compressors are used for partial product accumulation. By use of booth algorithm to generate partial product, speed of pipeline multiplier has been improved. Achieved delay and power consumption for 64 bit adder under supply voltage of 1.3V and 2GHz frequency are 112ps and 12mw, respectively and for multiplier, delay and power consumption are 291ps and 950mw. The presented structures have been implemented in TSMC 130nm CMOS technology.

In this paper, a biosensor has been fabricated using ZnO nanorods and nanoparticles to detect different concentrations of the E. coli bacteria. The innovation of this paper lies in design and fabrication of the resistive type E Coli bacteria sensor. To make this biosensors, printed circuit board based electrodes are designed and made in an interdigitated shape. Both hydrothermal and drop cast methods have been used to grow zinc oxide nanorods and to form a layer of zinc oxide nanoparticles on copper electrodes, respectively. By using these biosensors, different concentrations of the E. coli bacteria in water are measured. When the sensor is in contact to the bacteria, the resistance is changed because of reactions with the zinc oxide. The biosensor output is provided as a voltage proportional to the resistance change between the interdigitated electrodes. The results have been measured for biosensors exposed to UV light. The effect of zinc oxide nanoparticles concentration and PCB dimensions on voltage and sensitivity of the biosensors are also investigated. The measurement results using the fabricated biosensors have been compared and the biosensor with the highest sensitivity has been introduced.

In this paper design and two dimensional (2D) simulation of a photonic crystal highly sensitive temperature sensor is presented. The 2D simulations are based on finite-difference time-domain (FDTD) method and are done using Rsoft software. The device is constructed using a cavity filled with the distilled water located in the center of the photonic crystal waveguide. The operation of the proposed sensor is investigated considering the thermal variations of the refractive index of the background material (Si) and the cavity’s filled material (the distilled water) and also the thermal expansion of the structure. It has been shown that the radii of the cavity and its surrounding holes have an important role in the performance of the device. It has been shown that the relationship between the temperature variation and the shift in the resonant wavelength of the cavity is linear. Based on the simulation results, the sensitivity, the quality factor and the transmission of the proposed sensor are 149.79 pm/c, 6105 and 0.6, respectively.

In this paper the design and three dimensions (3D) simulation of a photonic crystal (PC) pressure sensor is presented. The device is based on a 2D PC slab of PbMoO4. The simulations are based on finite element method (FEM) and finite-difference time-domain (FDTD) method and are done using CST STUDIO SUITE software. The sensitivity of the proposed sensor is calculated by considering the deformation and also refractive index variation factors. The numerical results show that when a pressure is applied, both factors cause to a reduction in the resonant wavelength of the transmission spectrum. It has been shown that the relationship between the applied pressure and the shift in the resonant wavelength of the cavity is linear. Based on the simulation results, the quality factor of the resonant peak of the transmission spectrum and the sensitivity of the proposed sensor are  -2.858 nm/GPa and 1040 , respectively.