Design of a Low-Power, High-Performance, and Soft-Error Immune Flip-flop for Nanometer Technologies

As CMOS transistors are scaling down to improve performance, vulnerability of digital logic circuits to soft errors caused by energetic particles are increasing. Flip-flops (FF) are of the main elements of sequential logic circuits that are very susceptive to single event upset (SEU) and single event multiple-node upset (SEMU). In this paper, a new FF circuit robust against transient faults of SEU and SEMU caused by high-energy particle strikes is designed and evaluated. In comparison with previous work, the proposed circuit offers a low design cost, while, it also has a high degree of robustness against SEU/SEMU. This achievement is discussed and also evaluated by the simulations carried-out. Simulation results reveal that, the proposed circuit offers 20% improvement in power consumption and also 31% in delay as compared to the well-known and widely used MS-DICE FF. The effects of process, voltage, and temperature (PVT) variations on the performance of the proposed FF are also investigated and it is shown that this circuit has a reliable operation in the presence of PVT variations as well.