A New High Level Model to Check CTL Properties in VHDL Environment

This paper describes the use of polynomial integer equations for high level model of digital circuits for property checking formal verification at this level. Most formal verification methods use low-level representations of a design like BDDs. BDD operations are not applicable to a large datapath because of large CPU time and memory usage. In our method, a behavioral state machine is represented by a list of integer equations, and RT level properties are directly applied to this representation. Furthermore, this method is applied to circuits without having to separate their data and control sections. For this implementation, we use a canonical form of integer equations, which simplifies equations instead of solving them. This paper compares our results with those of the VIS verification tool that is a BDD based program.